// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
// All rights reserved.
// 
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
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//       from this software without specific prior written permission.
//     - The use of this software may or may not infringe the patent rights
//       of one or more patent holders.  This license does not release you
//       from the requirement that you obtain separate licenses from these
//       patent holders to use this software.
//     - Use of the software either in source or binary form, must be run
//       on or directly connected to an Analog Devices Inc. component.
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module system_top (

  // fmc fpga interface

  eth_rx_clk,
  eth_rx_cntrl,
  eth_rx_data,
  eth_tx_clk_out,
  eth_tx_cntrl,
  eth_tx_data,
  eth_mdc,
  eth_mdio_i,
  eth_mdio_o,
  eth_mdio_t,
  eth_phy_resetn,

  // phy interface

  phy_resetn,
  phy_rx_clk,
  phy_rx_cntrl,
  phy_rx_data,
  phy_tx_clk_out,
  phy_tx_cntrl,
  phy_tx_data,
  phy_mdc,
  phy_mdio);

  // fmc fpga interface

  output            eth_rx_clk;
  output            eth_rx_cntrl;
  output  [  3:0]   eth_rx_data;
  input             eth_tx_clk_out;
  input             eth_tx_cntrl;
  input   [  3:0]   eth_tx_data;
  input             eth_mdc;
  output            eth_mdio_i;
  input             eth_mdio_o;
  input             eth_mdio_t;
  input             eth_phy_resetn;

  // phy interface

  output            phy_resetn;
  input             phy_rx_clk;
  input             phy_rx_cntrl;
  input   [  3:0]   phy_rx_data;
  output            phy_tx_clk_out;
  output            phy_tx_cntrl;
  output  [  3:0]   phy_tx_data;
  output            phy_mdc;
  inout             phy_mdio;

  // simple pass through

  assign eth_rx_clk = phy_rx_clk;
  assign eth_rx_cntrl = phy_rx_cntrl;
  assign eth_rx_data = phy_rx_data;

  assign phy_tx_clk_out = eth_tx_clk_out;
  assign phy_tx_cntrl = eth_tx_cntrl;
  assign phy_tx_data = eth_tx_data;

  assign phy_mdc = eth_mdc;
  assign phy_mdio = (eth_mdio_t == 1'b0) ? eth_mdio_o : 1'bz;
  assign eth_mdio_i = phy_mdio;

  assign phy_resetn = eth_phy_resetn;

endmodule

// ***************************************************************************
// ***************************************************************************
